Semiconductor memories are used to store information, often in conjunction with microprocessors. Typical memory devices are comprised of an array of memory cells together with various "peripheral" circuitry. Each memory cell is capable of storing usually just one datum, typically in binary format, a "1" or "0." The memory cells are arranged in rows and columns. Each row of memory cells corresponds to and is accessible by a word line, and each column of memory cells corresponds to and is accessible by bit lines, often a pair of bit lines. At or near each intersection of each row and bit line in the array is a respective memory cell. In order to write or read from a specific memory cell, the memory device must be told which cell to access. This is done by reading an address and decoding it into a row address and a column address. The row address is used to locate and activate the word line along which the specific memory cell resides. By activating the word line, all the memory cells associated with the row are coupled to their respective bit lines. The column address then allows only the bit line (pair) for the selected memory cell to be coupled to the data line pair, with the appropriate data being transferred between the two. In the case of a memory read, data will be transferred from the memory cells to the data lines. In the case of a memory write, the data will be transferred from the data lines to the memory cell. In this way, a specific memory cell is coupled to the data lines during a memory access.
During a memory read, the signal read from a memory cell creates a voltage differential. The voltage differential is small, typically in the range of 100-200 mV. Because the differential is small, it needs to be amplified before it can be used by the logic circuits in the stages that follow. The amplification is achieved, often in multiple stages, by sense amplifiers. If the amplifier inputs are connected to data lines, the amplifier is called a sense amplifier. If the amplifier inputs are connected to bit lines, the amplifier is a sense amplifier often called a pre-sense amplifier.
Conventional sense amplifiers sense the voltage differential between the two input lines and amplify it. However, because bit lines and data lines are capacitively loaded, there is a delay in transmitting an applied voltage differential to the sense amplifiers. This results in an overall increase in the time required to read data from a memory cell.
While the voltage responds slowly, the current changes almost instantly. Because of this, current sensing differential amplifiers have been developed, which sense current differentials between two input lines, as opposed to voltage differentials. In this way, circuits can respond much more quickly to changes on bit lines or data lines. A good description of current sensing differential amplifiers is provided in U.S. Pat. No. 4,766,333 owned by Inmos Corporation and entitled "Current Sensing Differential Amplifiers" the disclosure of which is incorporated hereby.
FIG. 1 shows a current sensing differential amplifier in the prior art and is an improvement over initial current sensing differential amplifiers. FIG. 1 shows an amplifier circuit 10 which includes a reference voltage circuit 11, a first input terminal 12, a second input terminal 14, a first negative feedback transistor 30, a second negative feedback transistor 32, with the remaining portion of the circuit generally acting as a voltage amplifier.
Input terminal 12 is coupled to the sources of p-channel transistors 22 and 24. Input 14 is coupled to the sources of p-channel transistors 26 and 28. The gates of transistors 22, 34, 26, and 44 and the drains of transistors 26 and 44 are connected to a first node 48. The gates of transistors 24, 28, 36, and 42 and the drains of transistors 24 and 42 are connected to a second node 46. The drain of transistor 22 is coupled to ground (a source voltage) through a load transistor 34 and a first output terminal 38. Similarly, the drain of transistor 28 is coupled to ground through a load transistor 36 and to a second output terminal 40. Node 46 is coupled to ground through a load transistor 42. Node 48 is similarly coupled to ground through a load transistor 44. Circuit 10 additionally includes two p-channel transistors 30 and 32. Transistor 30 couples first input terminal 12 to VCC (a second source voltage). Transistor 32 couples second input terminal 14 to VCC. Transistors 30 and 32 serve as impedance loads to sense changes in the memory array being applied to input terminal 12 and 14. The gates of transistors 30 and 32 are coupled to output terminals 38 and 40, respectively. By coupling the gates of both transistors 30 and 32 to the output terminals, both transistors 30 and 32 provide negative feedback to insure both input terminals are kept relatively close in terms of voltage. Negative feedback will be discussed in more detail infra.
The relative sizes of transistors 22, 24, 26 and 28 as well as the relative sizes of transistors 34, 36, 42 and 44 are important. The channels of transistors 22, 24, 26 and 28 are quite large so they can be biased in saturation, draw lots of current, and be insensitive to variations in current and voltage across their drains and sources. The channels of transistors 34, 36, 42 and 44 are smaller, so they are sensitive to changes in current and voltage across their drains and sources.
Current sensing amplifier circuit 10 operates by receiving (as inputs) signals from a pair of data lines (or bit lines). Assume a starting state of data "0" is initially present on the data lines. The voltage of input 12 is less than the voltage of input 14. As the data state changes, due to an address change or similar event, the voltage of input 12 will attempt to rise or become greater than the voltage of input 14, which will attempt to fall. The voltage change will be slow due to a large line capacitance present on the data lines. If the sense amplifier were to react to a voltage change, the output would similarly respond slowly. While the voltages change very slowly, the currents being driven by the data lines change almost instantly.
As the voltage at the data line connected to input 14 tries to fall, it will cause current to flow away from the amplifier circuit into the data line. Because the voltage remains unchanged on input 14 due to the capacitance, the voltage from drain to source and the voltage from gate to source of transistor 32 remain unchanged. Consequently, current supplied through transistor 32 will also remain unchanged. The extra current being drawn away from the circuit through input 14 results in less current flowing through transistors 26 and 28. The current flowing through transistor 44 will similarly drop, because the current through transistor 44 equals the current through transistor 26.
Circuit 10 has been designed so that the size of transistors 36 and 44 have smaller channels that are more sensitive to changes in both current and voltage. This means that their width/length ratio is smaller. The smaller ratio gives a transistor a higher impedance when conducting. Because of the higher impedance in transistor 44, the voltage across transistor 44 will drop to a greater degree in response to a current drop. This results in the voltage of internal reference node 48 dropping. Because transistor 26 is relatively large, operating in saturation, internal reference node 48 can drop a large amount without affecting the current through transistor 26 or the voltage at input 14.
As the voltage of internal reference node 48 decreases, the gate to source voltage of transistor 34 also decreases. This allows the voltage of output 38 to rise. The gate to source voltage of transistor 22 increases, but because the size of transistor 22 is relatively large, it remains in saturation and the voltage of output 38 can rise without affecting the operation of transistor 22.
Similar to the voltage of input 14, the voltage of input 12 will be slow to change because of the high capacitance associated with the data lines. This results in transistor 30 continuing to supply the same amount of current. The extra current available from the reduced current consumption of input 12 will be supplied to transistors 22 and 24. The current increase in transistor 24 will cause an increase in the current of transistor 42. The sizing of the channel of transistor 42 will cause the voltage of internal reference node 46 to rise. The increase in voltage on internal reference node 46 will cause output 40 to be coupled more strongly to ground through transistor 36.
In this way, a voltage differential is seen on outputs 38 and 40 in response to changes in current at inputs 12 and 14.
Circuit 10 additionally includes negative feedback supplied by transistors 30 and 32. For example, as the voltage of output 40 decreases as a result of input 14 drawing more current, the gate to source voltage of transistor 32 increases. This turns transistor 32 on harder, which influences the voltage of input 14 upward. This is opposite to the influence being exerted by the data lines. This keeps the voltage differential between input 12 and input 14 to a minimum. By keeping the voltage differential of inputs 12 and 14 to a minimum, future switches occur much more quickly and easily.
However, circuit 10 does have inherent qualities that degrade switching performance. During the switching described above, the voltage of internal reference node 46 increases as a result of increased current through transistor 42. As internal reference node 46 increases in voltage, the gate to source voltage of transistor 42 increases. This causes transistor 42 to turn on harder, reducing the resistance through transistor 42 with which internal reference node 46 is coupled to ground. This is negative feedback associated with the internal reference nodes and reduces the speed at which the circuit can switch by limiting the speed at which the voltage of internal reference node 46 can rise. Internal reference node 48 is similarly affected in the opposite direction.
It is therefore an object of the invention to provide an improved current source amplifier by removing the negative feedback associated with the internal reference nodes, and changing it into positive feedback in order to accelerate the amplifier switching times.